매니 코어 기반 패킷 프로세서 디자인 이슈

Abundant parallelism in packet processing applications has taken advantage of the many-core processor technology to process hundreds of millions of packets per second. However, integrating hundreds of processor cores and increasing packet processing complexity pose many challenges in designing a many-core based packet processor. In this paper, we discuss design issues and current solutions to exiting problems. First, two processor array architectures are compared. Second, we discuss how to optimize the processor core features such as threading, special instructions, on-chip cache architecture from a packet processing perspective. Third, we discuss a high-performance QoS-aware memory system to process several hundred Gbps multi-class packet stream. Fourth, accessing shared data in the many-core based system could cause a serious performance problem. Various methods to maintain cache coherency and lock the critical section will be discussed. In addition to current issues and solutions, we present future design challenges assuming the process technology continuously scales and software designers add more complexity to the packet processing software. We discuss the scalability of cache coherency protocols and locking methods as the number of cores reaches a few thousands and how to deal with a heterogeneous processor core architecture proposed for a cost reduction.