Characterization of Stress-Induced p+/n Junction Leakage Failure for Sub-0.15- m CMOS Technology

Characterization of the dependence of n+/p and p+/n junction leakage on the line width and space has been performed for 0.15- m CMOS technology. The leakage current of a n+/p junction depends on the line width and the space while that of a p+/n junction shows a relatively smaller dependence on the line space. However, due to the formation of a Schottky contact, an abnormal increase in the leakage current occurs for a line width 0.2 m in the case of a p+/n junction. The SEM data show penetration of silicide into the substrate at the shallow trench isolation (STI) edge, which is proven to be due to the silicide and the STI mechanical stress. A pre-amorphization implant (PAI) process successfully improved the stress-induced p+/n leakage current and showed good silicide morphology. Therefore, suppressing the mechanical stress due to STI highly important when scaling down the device size, i.e., the active width for high performance, high density CMOS technology.