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학술논문Journal of Electromagnetic Engineering and Science2008.09 발행

A 3~5 GHz UWB Up-Mixer Block Using 0.18-μm CMOS Technology

A 3~5 GHz UWB Up-Mixer Block Using 0.18-μm CMOS Technology

김창완(동아대학교)

8권 3호, 91~95쪽

초록

This paper presents a direct-conversion I/Q up-mixer block, which supports 3~5 GHz ultra-wideband(UWB) applications. It consists of a VI converter, a double-balanced mixer, a RF amplifier, and a differential-to-single signal converter. To achieve wideband characteristics over 3~5 GHz frequency range, the double-balanced mixer adopts a shunt-peaking load. The proposed RF amplifier can suppress unwanted common-mode input signals with high linearity. The proposed direct-conversion I/Q up-mixer block is implemented using 0.18 μm CMOS technology. The measured results for three channels show a power gain of —2~—9 dB with a gain flatness of 1 dB, a maximum output power level of —7~—14.5 dBm, and a output return loss of more than —8.8 dB. The current consumption of the fabricated chip is 25.2 mA from a 1.8 V power supply.

Abstract

This paper presents a direct-conversion I/Q up-mixer block, which supports 3~5 GHz ultra-wideband(UWB) applications. It consists of a VI converter, a double-balanced mixer, a RF amplifier, and a differential-to-single signal converter. To achieve wideband characteristics over 3~5 GHz frequency range, the double-balanced mixer adopts a shunt-peaking load. The proposed RF amplifier can suppress unwanted common-mode input signals with high linearity. The proposed direct-conversion I/Q up-mixer block is implemented using 0.18 μm CMOS technology. The measured results for three channels show a power gain of —2~—9 dB with a gain flatness of 1 dB, a maximum output power level of —7~—14.5 dBm, and a output return loss of more than —8.8 dB. The current consumption of the fabricated chip is 25.2 mA from a 1.8 V power supply.

발행기관:
한국전자파학회
분류:
전자/정보통신공학

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A 3~5 GHz UWB Up-Mixer Block Using 0.18-μm CMOS Technology | Journal of Electromagnetic Engineering and Science 2008 | AskLaw | 애스크로 AI