Design of a 0.18-μm Logic Well-based nEDMOS and Improvement of Electrical Characteristics

An improved 0.18-μm logic well-based V_(GS) = 5 V extended drain NMOSFET (nEDMOST) has been designed, using TCAD (technology computer-aided design) simulation. Compared to a conventional EDMOS, the improved EDMOS proves to be an excellent candidate for high-performance and low-power applications. Also, the improved EDMOS has very low specific on-resistance R_(sp) = 7.45 [mΩ-mm^2] for the breakdown voltage, BVDSS = 15 V at V_(GS) = 0 V, and higher snapback breakdown voltage, BVDSN = 17 V at V_(GS) = 5 V, for a wider SOA (safe operating area) than the conventional one. TCAD simulations show that BVDSS of the improved EDMOS can be raised to 20 V while maintaining a low Rsp at a fixed pitch size L_(pitch) = 1.98 μm.