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학술논문대한임베디드공학회논문지2016.08 발행KCI 피인용 3

기약 AOP를 이용한 GF(2m)상의 낮은 지연시간의 시스톨릭 곱셈기

Low Latency Systolic Multiplier over GF(2m)Using Irreducible AOP

김기원(단국대학교); 한승철(명지대학교)

11권 4호, 227~233쪽

초록

Efficient finite field arithmetic is essential for fast implementation of error correcting codes and cryptographic applications. Among the arithmetic operations over finite fields, the multiplication is one of the basic arithmetic operations. Therefore an efficient design of a finite field multiplier is required. In this paper, two new bit-parallel systolic multipliers for GF(2m) fields defined by AOP(all-one polynomial) have proposed. The proposed multipliers have a little bit greater space complexity but save at least 22% area complexity and 13% area-time (AT) complexity as compared to the existing multipliers using AOP. As compared to related works, we have shown that our multipliers have lower area-time complexity, cell delay, and latency. So, we expect that our multipliers are well suited to VLSI implementation.

Abstract

Efficient finite field arithmetic is essential for fast implementation of error correcting codes and cryptographic applications. Among the arithmetic operations over finite fields, the multiplication is one of the basic arithmetic operations. Therefore an efficient design of a finite field multiplier is required. In this paper, two new bit-parallel systolic multipliers for GF(2m) fields defined by AOP(all-one polynomial) have proposed. The proposed multipliers have a little bit greater space complexity but save at least 22% area complexity and 13% area-time (AT) complexity as compared to the existing multipliers using AOP. As compared to related works, we have shown that our multipliers have lower area-time complexity, cell delay, and latency. So, we expect that our multipliers are well suited to VLSI implementation.

발행기관:
대한임베디드공학회
DOI:
http://dx.doi.org/10.14372/IEMEK.2016.11.4.227
분류:
내장형시스템

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기약 AOP를 이용한 GF(2m)상의 낮은 지연시간의 시스톨릭 곱셈기 | 대한임베디드공학회논문지 2016 | AskLaw | 애스크로 AI