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학술논문시스템엔지니어링학술지2021.12 발행

Development of an Intellectual Property Core for Floating Point Calculation for Safety Critical MMIS

Development of an Intellectual Property Core for Floating Point Calculation for Safety Critical MMIS

Nelson Josephat Mwilongo(KINGS); 정재천(한국전력국제원자력대학원대학교)

17권 2호, 37~48쪽

초록

Improving the plant protection system against unforeseen changes/transients during operation is essential to maintain plant safety. Under this condition, it requires rapid and accurate signal processing. The use of an Intellectual Property (IP) core for floating point calculations for Safety Critical MMIS can make numerical computations easier and more precise, improving system accuracy. It can represent and manipulate rational numbers as well as a much broader range of values with dynamic range in nuclear power plant. Systems engineering approach (SE) is used through the development process, it helps to reduce complexity and avoid omissions and invalid assumptions as delivers a better understanding of the stakeholders needs. For the implementation on the FPGA target board, the 32-bit floating-point arithmetic with IEEE-754 standards has designed using Simulink model in Matlab for all operations of addition, subtraction, multiplication and division and VHDL code generated.

Abstract

Improving the plant protection system against unforeseen changes/transients during operation is essential to maintain plant safety. Under this condition, it requires rapid and accurate signal processing. The use of an Intellectual Property (IP) core for floating point calculations for Safety Critical MMIS can make numerical computations easier and more precise, improving system accuracy. It can represent and manipulate rational numbers as well as a much broader range of values with dynamic range in nuclear power plant. Systems engineering approach (SE) is used through the development process, it helps to reduce complexity and avoid omissions and invalid assumptions as delivers a better understanding of the stakeholders needs. For the implementation on the FPGA target board, the 32-bit floating-point arithmetic with IEEE-754 standards has designed using Simulink model in Matlab for all operations of addition, subtraction, multiplication and division and VHDL code generated.

발행기관:
한국시스템엔지니어링학회
DOI:
http://dx.doi.org/10.14248/JKOSSE.2021.17.2.037
분류:
시스템엔지니어링

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Development of an Intellectual Property Core for Floating Point Calculation for Safety Critical MMIS | 시스템엔지니어링학술지 2021 | AskLaw | 애스크로 AI