Low Complexity Bit-Parallel Systolic Polynomial Basis Multiplier over Finite Fields GF(2m)

Finite field operations are essential in error-correcting codes and public key cryptosystems. Multiplication is main finite field operation in cryptographic computations and designing efficient multiplier affect the performance of cryptosystems. In this paper, we consider a low complexity bit-parallel semi-systolic multiplier to facilitate more efficient parallel computation by dividing Montgomery multiplication (MM) into two identical and independent components, along with two level systolic computation architecture. The proposed multiplier consists of an most significant bit (MSB)-first general multiplication systolic array and an least significant bit (LSB)-first Montgomery multiplication systolic array. These two uniformly partitioned arrays can be executed independently in an LSB-first structure, making them well-suited for implementation on a single array. The efficiency of our research is demonstrated by the lowered AT complexity as compared to related works. The proposed multiplier architecture achieves regularity, modularity, and concurrency which are important attributes of VLSI implementation.